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78k0/kd2 mos integrated circuit preliminary product information 8-bit single-chip microcontroller ?nec electronics corporation 2004 this information contained in this document is being issued in advance of the production cycle for the product. the parameters for the product may change before final produc tion or nec electronics corporation, at its own discretion,, may withdraw the product prior to its production. not all pr oducts and/ or types are available in every country. please check with an nec electronics sales representative for availability and additional information. zud-cc-04-0127-e data published oct 2004 n cp(k) the 78k0/kd2 products are 8-bit single-chip microcontrollers of the 78k0 series. these microcontrollers feature single-voltage self -programming flash memory and many peripherals. features ? 78k0 cpu core, 8-bit cisc architecture ? flash eeprom and ram sizes item product name program memory (flash eeprom) data memory (ram) pd78f0527 128k bytes (flash) 7k bytes pd78f0526 96k bytes (flash) 5k bytes pd78f0525 60k bytes (flash) 3k bytes pd78f0524 48k bytes (flash) 2k bytes pd78f0523 32k bytes (flash) 1k bytes pd78f0522 24k bytes (flash) 1k bytes pd78f0521 16k bytes (flash) 768 bytes minimum instruction cycle 0.1 s (20mhz@4.0v to 5.5v) 0.2 s (10mhz@2.7v to 5.5v) 0.4 s ( 5mhz@1.8v to 5.5v) clock ? main clock - internal ring-oscillator 8mhz (typ.) - ceramic/crystal oscillator/external clk (2mhz to 20mhz) (instruction execution ti me = 100ns(min.) @20mhz) ? sub clock - 32.768khz crystal oscillator/ external clk ? wdt clock - internal ring-oscillator 240khz (typ.) peripherals . ? on-chip power-on-clear (poc) circuit ? low - voltage detector (lvi) circuit ? timer - 16bit timer 1ch - 8bit timer 4ch - watch timer - watchdog timer (operable with 240khz ring-osc) ? serial interface - uart/csi 1ch - uart (with lin-bus) 1ch - iic 1ch ? key interrupt 8ch ? ad converter - 10-bit resolution a/d converter 8ch ? i/o port total : 45 cmos i/o : 40 cmos output: 1 n-ch o.d i/o: 4 ? multuplier/divider - 16 bit x 16bit, 32bit / 16bit ( pd78f0524/0525/0526/0527 only) ? other - self programming ?e - pcl output - on-chip debug function (p roduct name is undecided ) interrupt - internal 16ch - external 8ch operation voltage 1.8v to 5.5v package 52-pin lqfp(10mm x 10mm, 0.65mm pitch)
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) 1. block diagram fig. 78k0/kd2 16bit timer (tm00) to00 ti000 ti010 8bit timer (tmh0) toh0 8bit timer (tmh1) toh1 uart-lin (uart6) rxd6 txd6 watchdog timer 78k0 cpu core ram reset reset ctl system control flmd0 regc vdd vss x1 x2/ exclk xt1 xt2/ exsclks internal high-speed ring-osc ( 8mhz t yp . ) 8bit timer (tm50) to50 ti50 8bit timer (tm51) to51 ti51 uart (uart0) rxd0 txd0 3wire serial i/f (csi10) sck10 si10 so10 port0 multi master iic (iic0) exscl0 scl0 sda0 watch timer (wt) 10bit ad converter avss avref ani0 - ani7 external interru p t intp0 - intp7 key return kr0 - kr7 exlvi low voltage indicator ( lvi ) p00 -p03 port1 p10 -p17 port2 p20 -p27 port3 p30 -p33 port4 p40 -p41 port6 p60 -p63 port7 p70 -p77 port12 p120 -p124 port13 p140 port14 p130 power on clear (poc) internal low-speed ring-osc ( 240khz t yp . ) high-speed system clock osc subsystem clock osc multiplier /divide* (16x16, 32/16) flash eeprom * ?f pd78f0527/0526/0525/0524 only clock output control pcl
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) 2. pin lay out 78k0/kd2 52-pin plastic lqfp (10 x 10mm 0.65mm pitch) pd78f0527gb-uet, pd78f0526gb-uet, pd78f0525gb-uet, pd78f0524gb-uet, pd78f0523gb-uet, pd78f0522gb-uet, pd78f0521gb-uet 52pin qfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 p140/pcl/intp6 p120/intp0/exlvi p41 p40 reset p124/xt2/exclks p123/xt1 ic/flmd0 p122/x2/exclk p121/x1 regc vss vss vdd vdd p60/scl0 p61/sda0 p62/exscl0 p63 p33/ti51/to51/intp4 p77/kr7 p76/kr6 p75/kr5 p74/kr4 p73/kr3 p72/kr2 p71/kr1 p70/kr0 p32/intp3 p31/intp2 p30/intp1 p17/ti50/to50 p16/toh1/intp 5 p15/toh0 p14/rxd6 p13/txd6 p12/so10 p11/si10/rxd0 p10/sck10/txd 0 avref avss p27/ani7 p26/ani6 p25/ani5 p24/ani4 p23/ani3 p22/ani2 p21/ani1 p20/ani0 p130 p03 p02 p01/ti010/to00 p00/ti000
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) 3. pin function table (1/2) pin name function vdd positive power supply except for ports (except p20-p27) and ad converter vss ground potential except for ports (except p20-p27) and ad converter reset system reset input flmd0 flash eeprom programming mode setting regc connecting regulator stabilization capacitor. connect to ground via a capacitor (0.47 f) avref a/d converter analog power supply and power supply for p20-p27 avss ground potential for a/d converter and p20 - p27. i/o port p00 /ti00 external count clock input to 16-bit timer/event counter 00 capture trigger input to capture registers (cr000, cr010) of16-bit timer/event counter 00 (tm00) i/o port capture trigger input to captur e register (cr000) of 16-bit timer/event counter 00 (tm00) p01 /ti010 /to00 16-bit timer/event counter 00 output (tm00) p02 i/o port p03 i/o port i/o port clock input/ output for serial interface (csi10) p10 /sck10 /txd0 serial data output from asynchronous serial interface (uart0) i/o port serial data inpu t to serial interface (csi10) p11 /si10 /rxd0 serial data input to asynchronous serial interface (uart0) i/o port p12 /so10 serial data output form serial interface (csi10) i/o port p13 /txd6 serial data output from asynchronous serial interface (uart6) i/o port p14 /rxd6 serial data input from asynchronous serial interface (uart6) i/o port p15 /toh0 8-bit timer h0 output (tmh0) i/o port 8-bit timer h1 output (tmh1) p16 /toh1 /intp5 external interrupt request input with specifiable valid edges i/o port external count clock input to 8- bit timer/event counter 50 (tm50) p17 /ti50 /to50 8-bit timer/event counter 50 output (tm50) p20- p27 / ani0- ani7 i/o ports a/d converter analog input p30/intp1 p31/intp2 p32/intp3 i/o port external interrupt request input with specifiable valid edges i/o port external count clock input to 8- bit timer/event counter 51(tm51) 8-bit timer/event counter 51output (tm51) p33 /ti51 /to51 /intp4 external interrupt request input with specifiable valid edges p40 - p41 i/o port
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) table(2/2) pin name function i/o port (n-ch open drain) p60 /scl0 clock input/ output for serial interface (iic0) i/o port (n-ch open drain) p61 /sda0 serial data input/ output fo r serial interface (iic0) i/o port (n-ch open drain) p62 /exscl0 external clock input for serial interface (iic0) p63 i/o port (n-ch open drain) i/o ports p70 ? p77 /kr0 ? kr7 key interrupt input i/o port external interrupt request input with specifiable valid edges p120 /intp0 /exlvi reference voltage input for low voltage indicator i/o port (an external oscillat ion circuit is not used) p121 /x1 connecting resonator for main system clock oscillation i/o port (an external oscillat ion circuit is not used) connecting resonator for main system clock oscillation p122 /x2 /exclk external clock input fo r main system clock i/o port (an external oscillat ion circuit is not used) p123 /xt1 connecting resonator for subsystem clock oscillation i/o port (an external oscillat ion circuit is not used) connecting resonator for subsystem clock oscillation p124 /xt2 /exclks external clock input for subsystem clock p130 output port i/o port clock output p140 /pcl /intp6 external interrupt request input with specifiable valid edge
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) 4. memory space 78k0/kd2 have 64kb linear address area. to access more than 64kb rom area, 96kb and 128kb rom products have bank type rom at address of 8000h to c000h. all bank rom size is 16kb. 5. clock 78k0/kd2 have 2 type internal ring-osc and 2 type external resonator oscillation circuit. 78k0/kd2 can be operated high-speed internal ring -osc only. low-speed ring-osc can connect to watch dog timer and 8bit timer (tmh1) only for high secure. common rom bank rom products rom size address address number of bank pd78f0527 128kb 0000h-7fffh (32kb) 8000h-bfffh (16kb) 6 pd78f0526 96kb 0000h-7fffh (32kb) 8000h-bfffh (16kb) 4 pd78f0525 60kb 0000h-efffh (60kb) - - pd78f0524 48kb 0000h-bfffh (48kb) - - pd78f0523 32kb 0000h-7fffh (32kb) - - pd78f0522 24kb 0000h-5fffh (24kb) - - pd78f0521 16kb 0000h-3fffh (16kb) - - low-speed ring-osc ( 240khz t y p ) high-speed ring-osc (8mhz typ) high-speed system clock oscillation circuit (2-20mhz) watchdog timer cpu peripheral subsystem clock oscillation circuit (32.768khz) mpx mpx watch timer pcl 8bit timer (tmh1) external resonator or external clock external resonator or external clock fig. clock connecting block image
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) 6. outline of functions of kd2 pd78f0521 pd78f0522 pd78f0523 flash memory 16 k 24 k 32 k bank - internal memory (byte) high speed ram 768 1k extend ram - ceramic/crystal - 2 to 20 mhz: v dd = 4.0 to 5.5 v - 2 to 10 mhz: v dd = 2.7 to 5.5 v - 2 to 5 mhz: v dd = 1.8 to 5.5 v main system clock internal ring-osc - 8 mhz(typ.) sub system clock - 32.768 khz(typ.) internal low speed ring-osc (for tmh1, wdt) - 240 khz(typ.) minimum instruction cycle - 0.1 s (ceramic/ crystal operation f xh = 20 mhz v dd = 4.0 to 5.5 v) i/o total :45 - cmos i/o :40 - cmos out :1 - n-ch o.d. :4 timer - 16 bit timer/event counter:1ch - 8 bit timer/event counter:2ch - 8 bit timer:2ch - watch timer:1ch - watch dog timer:1ch timer output -5(pwm:3) pcl output - 156.25khz, 312.5khz, 615khz , 1.25mhz, 2.5mhz, 5mhz, 10mhz (f prs = 20 mhz) buzzer output - a/d converter - 10bit x 8ch serial interface - uart (with lin-bus):1ch - csi/ uart:1ch - i 2 c:1ch multiplier/divider - internal 16 interrupt external 8 key return 8ch on chip debug function product name is undecided. voltage range v dd = 1.8 to 5.5 v operation temperature ta = -40 c to +85 c package - 52pin lqfp(10x10) 0.65mm pitch
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) pd78f0524 pd78f0525 pd78f0526 pd78f0527 flash memory 48 k 60 k 96 k 128 k bank - - 4 6 internal memory (byte) high speed ram 1k extend ram 1 k 2 k 4 k 6 k ceramic/crystal - 2 to 20 mhz: v dd = 4.0 to 5.5 v - 2 to 10 mhz: v dd = 2.7 to 5.5 v - 2 to 5 mhz: v dd = 1.8 to 5.5 v main system clock internal ring-osc - 8 mhz(typ.) sub system clock - 32.768 khz(typ.) internal low speed ring-osc (for tmh1, wdt) - 240 khz(typ.) minimum instruction cycle - 0.1 s (ceramic/ crystal operation f xh = 20 mhz v dd = 4.0 to 5.5 v) i/o total :45 - cmos i/o :40 - cmos out :1 - n-ch o.d. :4 timer - 16 bit timer/event counter:1ch - 8 bit timer/event counter:2ch - 8 bit timer:2ch - watch timer:1ch - watch dog timer:1ch timer output -5(pwm:3) pcl output - 156.25khz, 312.5khz, 615khz , 1.25mhz, 2.5mhz, 5mhz, 10mhz (f prs = 20 mhz) buzzer output - a/d converter - 10bit x 8ch serial interface - uart (with lin-bus):1ch - csi/ uart:1ch - i 2 c:1ch multiplier/divider 16bitx16bit, 32bit/8bit internal 16 interrupt external 8 key return 8ch on chip debug function product name is undecided. voltage range v dd = 1.8 to 5.5 v operation temperature ta = -40 c to +85 c package - 52pin lqfp(10x10) 0.65mm pitch
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) 7. electrical specification of kd2 (target) caution ? these specifications show target values, which may change after device evaluation. the operating voltage range may also change. absolute maximum ratings(t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd -0.5 to +6.5 v v ss -0.5 to +0.3 v av ref -0.5 to +6.5 v supply voltage av ss -0.5 to +0.3 v v i1 -0.3 to v dd +0.3 note v input voltage v i2 p60-p63(n-ch open drain) -0.3 to +6.5 v output voltage v o -0.3 to v dd +0.3 note v analog input voltage v an -0.3 to av ref +0.3 note v per pin -10 ma p00-p03, p40-p41, p120-p124, p130, p140 -25 ma output current, high i oh total of all pins -80 ma p10-p17,p30-p33, p60-p63, p70-p77 -55 ma note must be 6.5 v or lower . caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristic s of alternate-function pins are the same as those of port pins.
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) absolute maximum ratings(t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin 30 ma p00-p03, p40-p41, p120-p124, p130, p140 60 ma output current, low i ol total of all pins 200 ma p10-p17,p30-p33, p60-p63, p70-p77 140 ma in normal operation mode operating ambient temperature t a in flash memory programming mode -40 to +85 c storage temperature t stg -65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristic s of alternate-function pins are the same as those of port pins.
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) high-speed system clock (crystal/c eramic) oscillator characteristics (t a = -40 to +85 c, 1.8 v v dd 5.5 v, 2.3 v av ref v dd , v ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 4.0 v v dd 5.5 v 2.0 20.0 2.7 v v dd < 4.0 v 2.0 10.0 ceramic resonator c1 x2 x1 v ss c2 oscillation frequency(f xh ) note 1.8 v v dd < 2.7 v 2.0 5.0 mhz 4.0 v v dd 5.5 v 2.0 20.0 2.7 v v dd < 4.0 v 2.0 10.0 crystal resonator oscillation frequency(f xh ) note 1.8 v v dd < 2.7 v 2.0 5.0 mhz note indicates only oscillator characte ristics. refer to ac characterist ics for instruction execution time. cautions 1. when using the high-speed system clock osc illator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. since the cpu is started by the ring-osc after reset is released, check the oscillation stabilization time of the high-speed system cl ock using the oscillation stabilization time status register (ostc). determine the oscilla tion stabilization time of the ostc register and oscillation stabilization time select regi ster (osts) after sufficiently evaluating the oscillation stabilization time wi th the resonator to be used. remark for the resonator selection and oscillator co nstant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufact urer for evaluation. c1 x2 x1 c2 v ss
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) ring-osc oscillato r characteristics (t a = -40 to +85 c, 1.8 v v dd 5.5 v, 2.3 v av ref v dd , v ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit 2.7 v v dd 5.5 v 7.6 note2 8.0 note2 8.4 note2 mhz 8 mhz ring-osc oscillator high-speed ring-osc oscillation frequency(f rh ) note1 1.8 v v dd 5.5 v t.b.d 8.0 note2 t.b.d mhz 2.7 v v dd 5.5 v 216 240 264 khz 240 khz ring-osc oscillator low-speed ring-osc oscillation frequency(f rl ) 1.8 v v dd 5.5 v t.b.d 240 t.b.d khz note 1. indicates only oscillator characteristics. refer to ac characteristics fo r instruction execution time. 2. this is the frequency in the case of rsts(rcm .7)=1. this is 5 mhz(typ.) in the case of rsts=0. subsystem clock oscilla tor characteristics (t a = -40 to +85 c, 1.8 v v dd 5.5 v, 2.3 v av ref v dd , v ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator oscillation frequency(f sub ) note 32 32.768 35 khz note indicates only oscillator characte ristics. refer to ac characte ristics for instruction execution time. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ?? 2. the subsystem clock oscilla tor is designed as a low-am plitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the high-speed system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufact urer for evaluation. 95 95 $ $ 3e v ss
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) dc characteristics (1/4) (t a = -40 to +85 c, 1.8 v v dd 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0v v dd 5.5v -3.0 2.7 v v dd < 4.0v -2.5 per pin of p00-p03, p10-p17, p30-p33, p40-p41, p70-p77, p120, p130, p140 1.8 v v dd < 2.7v -1.0 ma 4.0v v dd 5.5v -20.0 2.7 v v dd < 4.0v -10.0 total of p00-p03, p40-p41, p120, p130, p140 1.8 v v dd < 2.7v -5.0 ma 4.0v v dd 5.5v -30.0 2.7 v v dd < 4.0v -19.0 total of p10-p17, p30-p33, p70-p77 1.8 v v dd < 2.7v -10.0 ma 4.0v v dd 5.5v -50.0 2.7 v v dd < 4.0v -29.0 i oh1 total of all pins 1.8 v v dd < 2.7v -15.0 ma output current, high i oh2 per pin of p20-p27, p121-p124 note 1.8 v v dd 5.5v -100 a 4.0v v dd 5.5v 8.5 2.7 v v dd < 4.0v 5.0 per pin of p00-p03, p10-p17, p30-p33, p40-p41, p70-p77, p120, p130, p140 1.8 v v dd < 2.7v 2.0 ma 4.0v v dd 5.5v 15.0 2.7 v v dd < 4.0v 5.0 per pin of p60-p63 1.8 v v dd < 2.7v 2.0 ma 4.0v v dd 5.5v 20.0 2.7 v v dd < 4.0v 15.0 total of p00-p03, p40-p41, p120, p130, p140 1.8 v v dd < 2.7v 9.0 ma 4.0v v dd 5.5v 45.0 2.7 v v dd < 4.0v 35.0 total of p10-p17, p30-p33, p70-p77 1.8 v v dd < 2.7v 20.0 ma 1.8 v v dd 5.5v 65.0 4.0v v dd 5.5v 50.0 i ol1 total of all pins 2.7 v v dd < 4.0v 29.0 ma output current, low i ol2 per pin of p20-p27 note 1.8 v v dd < 2.7v 400 a note ? when used as digital input ports, set av ref = v dd . caution this specification is duty = 70% condition of i oh and i ol . remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) dc characteristics (2/4) (t a = -40 to +85 c, 1.8 v v dd 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v ih1 p02, p12, p13, p15, p40-p41, p60-p63, p121-p124 0.7v dd v dd v v ih2 p00, p01, p03 p10-p11, p14, p16-p17, p30-p33, p70-p77, p120, p140, reset 0.8v dd v dd v input voltage, high v ih3 p20-p27 note 0.7av ref av ref v v il1 p02, p12, p13, p15, p40-p41, p60-p63, p121-p124, 0 0.3v dd v v il2 p00, p01, p03 p10-p11, p14, p16-p17, p30-p33, p70-p77, p120, p140, reset 0 0.2v dd v input voltage, low v il3 p20-p27 note 0 0.3av ref v note ? when used as digital input ports, set av ref = v dd . remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) dc characteristics (3/4) (t a = -40 to +85 c, 1.8 v v dd 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit i oh = -3.0 ma 4.0v v dd 5.5v v dd -0.7 v i oh = -2.5 ma 2.7 v v dd 5.5v v dd -0.5 v v oh1 i oh = -1.0 ma p00-p03, p10-p17, p30-p33, p40-p41, p70-p77, p120, p130, p140 1.8 v v dd 5.5v v dd -0.5 v output voltage, high v oh2 i oh = -100 a p20-p27 1.8 v v dd 5.5 v av ref = v dd v dd -0.5 v i ol = 8.5 ma 4.0v v dd 5.5v 0.7 v i ol = 1.0 ma 2.7 v v dd 5.5v 0.5 v v ol1 i ol = 0.5 ma p00-p03, p10-p17, p30-p33, p40-p41, p70-p77, p120, p130, p140 1.8 v v dd 5.5v 0.4 v v ol2 i ol = 400 a p20-p27 1.8 v v dd 5.5 v av ref = v dd 0.4 v i ol = 15.0 ma 2.0 v i ol = 5.0 ma 4.0v v dd 5.5v 0.4 v i ol = 3.0 ma 2.7 v v dd 5.5v 0.4 v output voltage, low v ol3 i ol = 2.0 ma p60-p63 1.8 v v dd 5.5v 0.4 v i lih1 v i = v dd p00-p03, p10-p17, p30-p33, p40-p41, p70-p77, p120-p124, p130, p140 1 a i lih2 v i = av ref p20-p27 1 a input leakage current, high i lih3 v i = v dd x1, x2, xt1, xt2 (when use external oscillator) 20 a i lil1 v i = v ss p00-p03, p10-p17, p30-p33, p40-p41, p70-p77, p120-p124, p130, p140 -1 a i lil2 v i = av ref p20-p27 -1 a input leakage current, low i lil3 v i = v ss x1, x2, xt1, xt2 (when use external oscillator) -20 a pull-up resistance value r u v i = v dd 10 20 100 k ? v il in normal operation mode 0 0.2v dd v flmd0 supply voltage v ih in flash memory programming mode 0.8v dd v dd v remark unless specified otherwise, the characteristic s of alternate-function pins are the same as those of port pins.
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) dc characteristics (4/4) (t a = -40 to +85 c, 1.8 v v dd 5.5 v, 2.3 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit f xh = 20 mhz note2 , v dd = 5.0 v 4.7 5.8 ma f xh = 10 mhz note 2 , v dd = 5.0 v note 3 2.5 3.5 ma f xh = 5 mhz note 2 , v dd = 3.0 v note3 1.5 2.2 ma f rh = 8 mhz note 2 , v dd = 5.0 v 1.9 2.7 ma i dd1 operation mode f sub = 32.768 khz note 2 , v dd = 5.0 v 17 t.b.d. a f xh = 20 mhz note 2 , v dd = 5.0 v 2.2 2.6 ma f xh = 10 mhz note 2 , v dd = 5.0 v note3 1.0 1.2 ma f xh = 5 mhz note2 , v dd = 3.0 v note3 0.55 0.65 ma f rh = 8 mhz note 2 , v dd = 5.0 v 0.6 0.65 ma i dd2 halt mode f sub = 32.768 khz note2 , v dd = 5.0 v 3.5 t.b.d. a i dd3 stop mode v dd = 5.0 v 1 20 a a/d converter operating 0.57 1.3 ma i adc a/d converter operating current a/d converter not operating t.b.d. t.b.d. ma i wdt watchdog time operating current 240 khz ring-osc operating 5 10 a supply current note 1 i lvi lvi operating current 9 t.b.d. a notes 1. total current flowing through the internal power supply (v dd ). 2. input square-wave 3. when amph(oscctl.0) = 0. remark 1. f xh : high-speed system clock oscillation fre quency (x1 clock oscillation frequency or external main system clock frequency). ?? 2. f rh : high-speed ring-osc oscillation frequency. ? 3. f sub : subsystem clock oscillation frequency (xt1 cl ock oscillation frequency or external subsystem clock frequency).
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) ac characteristics (1)basic operation (t a = -40 to +85 c, 1.8 v v dd 5.5 v, 2.3 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 0.1 16 s 2.7 v v dd < 4.0 v 0.2 16 s high-speed system clock(f xh ) 1.8 v v dd < 2.7 v 0.4 16 s 2.7 v v dd < 5.5 v 0.25 4 s main system clock(f xp ) operation high-speed ring-osc clock(f rh ) 1.8 v v dd < 2.7 v 0.5 4 s instruction cycle (minimum instruction execution time) t cy subsystem clock(f sub )operation 114 122 125 s 4.0 v v dd 5.5 v 2.0 20.0 mhz 2.7 v v dd < 4.0 v 2.0 10.0 mhz external main system clock frequency f exclk 1.8 v v dd < 2.7 v 2.0 5.0 mhz external main system clock input high-/low-level width t exclkh , t exclkl (1/ f exclk x 1/2) - 1 ns external subsystem clock frequency f exclks 32 32.768 35 khz external subsystem clock input high-/low-level width t exclksh , t exclksl (1/ f exclks x 1/2) - 5 ns 4.0 v v dd 5.5 v 2/f sam + 0.1 note1 s ti000, ti010 i nput high-level width, low-level width t tih0 , t til0 2.7 v v dd < 4.0 v 2/f sam + 0.2 note1 s 4.0 v v dd 5.5 v 10 mhz 2.7 v v dd < 4.0 v 10 mhz ti50, ti51 input frequency f ti5 1.8 v v dd < 2.7 v 5 mhz 4.0 v v dd 5.5 v 50 ns 2.7 v v dd < 4.0 v 50 ns ti50, ti51 input high-level width, low-level width t tih5 , t til5 1.8 v v dd < 2.7 v 100 ns interrupt input high-level width, low-level width t inth , t intl 1 s key return input low-level width t kr 250 ns reset low-level width t rsl 10 note2 s notes 1. selection of f sam = f prs , f prs /4, f prs /256 is possible using bits 0 and 1 (prm000, prm001) of prescaler mode register (prm00). note that when selecting the ti000 valid edge as the count clock, f sam = f prs . 2. input low level signal into reset pin until powe r supply voltage is stabilized in the case of the power supply voltage rise time is slowly (more than 3.4ms).
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) t cy vs v dd (main system clock operation) guaranteed operation range supply voltage v dd [v] remark the values indicated by the shaded secti on are only when the high-speed ring-osc clock is selected. [
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) ac timing test points (excluding x1 input) 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd clock timing x1 input v ih6 (min.) v il6 (max.) 1/f xp t xpl t xph 1/f xt t xtl t xth xt1 input v ih6 (min.) v il6 (max.) ti timing ti000, ti010 t til0 t tih0 ti50, ti51 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp7 t intl t inth reset input timing reset t rsl
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) (2) serial interface (t a = -40 to +85 c, 1.8 v v dd 5.5 v, 2.3 v av ref v dd , v ss = av ss = 0 v) (a)uart mode (uart6, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbps (b) uart mode (uart0, dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 312.5 kbps (c) iic0 mode normal mode high speed mode parameter symbol min. . max min. . max unit scl0 clock frequency f clk 0 100 0 400 khz start/restart condition setup time note1 t su: sta 4.8 - 0.7 - s hold time t hd: sta 4.1 - 0.7 - s hold time in scl = ?l? t low 5.0 - 1.25 - s hold time in scl = ?h? t high 5.0 - 1.25 - s data setup time (reception) t su: dat 0 - 0 - s data hold time (sending) note2 t hd: dat 0.47 4.0 0.23 1.00 s notes 1. the first clock pulse is generated after this perio d in the case of the start/restart condition. 2. the max of t hd:dat is normal transition value. wait is occurred in the term of ack(acknowledge) . caution specification at 1.8 v v dd < 2.7v is not fixed .
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) (d) 3-wire serial i/o mode (csi10 master mode, sck1n ? internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 100 ns sck1n cycle time t kcy1 2.7 v v dd < 4.0 v 200 ns sck1n high-/low-level width t kh1 , t kl1 t kcy1 /2 - 10 not1 ns si1n setup time (to sck1n ) t sik1 30 ns si10hold time (to sck1n ) t ksi1 30 ns delay time from sck1n to so1n output t kso1 c = 50 pf note2 40 ns notes 1. this is the value when the high-speed system clock (f xh ) is operating. ? 2. c is the load capacitance of the sck1n and so1n output lines. (e) 3-wire serial i/o mode (csi10 slave mode, sck1n ? external clock input) parameter symbol conditions min. typ. max. unit sck1n cycle time t kcy2 400 ns sck1n high-/low-level width t kh2 , t kl2 t.b.d ns si1n setup time (to sck1n ) t sik2 80 ns si1n hold time (to sck1n ) t ksi2 50 ns delay time from sck1n to so1n output t kso2 c = 50 pf note 120 ns note c is the load capacitance of the so1n output lines. remark n = 0 caution specification at 1.8 v v dd < 2.7v is not fixed .
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) serial transfer timing 3-wire serial i/o mode: si1n so1n t kcym t klm t khm t sikm t ksim input data t ksom output data sck1n remark m = 1, 2 n = 0
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) a/d converter characteristics (t a = -40 to +85 c | 1.8 v v dd 5.5 v, 2.3 v av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es 10 bit 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref 5.5 v 0.6 %fsr overall error note1,2 a inl av ref < 2.7 v t.b.d. %fsr 4.0 v av ref 5.5 v 6.6 30 s 2.7 v av ref 5.5 v 6.6 30 s conversion time t conv av ref < 2.7 v 11 t.b.d. s 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref 5.5 v 0.6 %fsr zero-scale error note1,2 e zs av ref < 2.7 v t.b.d. %fsr 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref 5.5 v 0.6 %fsr full-scale error note1,2 e fs av ref <2.7 v t.b.d. %fsr 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref 5.5 v 4.5 lsb integral linearity error note1 i le av ref < 2.7 v t.b.d. lsb 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref 5.5 v 2.0 lsb differential linearity error note1 d le av ref < 2.7 v t.b.d. %fsr analog input voltage v ain av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. poc circuit characteristics (t a = -40 to +85 c) parameter symbol conditions min. typ. max. unit detection voltage v poc 1.3 1.5 1.7 v power supply rise time t pth v dd : v poc 1.8 v (min. value of v dd ) 75 t.b.d mv/ms minimum pulse width t pw t.b.d. 50 s notes 1. when voltage rises, time required from detection to reset release 2. when voltage drops, time required from detection to reset occur. poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pthd t pw t pd
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) lvi circuit characteristics (t a = -40 to +85 c) parameter symbol conditions min. typ. max. unit v lvi0 4.10 4.20 4.30 v v lvi1 3.95 4.05 4.15 v v lvi2 3.81 3.91 4.01 v v lvi3 3.66 3.76 3.86 v v lvi4 3.51 3.61 3.71 v v lvi5 3.37 3.47 3.57 v v lvi6 3.22 3.32 3.42 v v lvi7 3.07 3.17 3.27 v v lvi8 2.93 3.03 3.13 v v lvi9 2.78 2.88 2.98 v v lvi10 2.63 2.73 2.83 v v lvi11 2.49 2.59 2.69 v v lvi12 2.34 2.44 2.54 v v lvi13 2.19 2.29 2.39 v v lvi14 2.05 2.15 2.25 v supply voltage level v lvi15 1.90 2.00 2.10 v detection voltage external input pin note1 exlvi exlvi < v dd 1.21 v minimum pulse width t lw t.b.d. 50 s operation stabilization wait time note2 t lwait1 10 t.b.d s note 1. ? using exlvi/p120/intp0 pin 2. time required from setting lvion to 1 to operation stabilization remark v lvi(n ?| 1) > v lvin : n = 1-15 lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t ld t wait1 lvion 1
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) data memory stop mode low supply voltage data retention characteristics (t a = -40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.3 note 5.5 v note dependence on poc detection voltage. the data is held before poc reset, but is not held after poc reset when voltage drops. stop instruction stop mode data retention mode standby release signal operation mode
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) flash memory programming characteristics (t a = -40 to +85 c, 2.3 v v dd 5.5 v, 2.3 v av ref v dd , v ss = av ss = 0 v) (1) basic characteristics parameter symbol conditions min. typ. max. unit v dd supply voltage i dd f xp = 10 mhz (typ.), 20 mhz (max.) 4.5 11.0 ma chip unit t eraca 20 t.b.d ms erase time note1 sector unit t erasa 20 t.b.d ms write time t wrwa 50. t.b.d. s number of rewrites per chip c erwr 1 erase + 1 write after erase = 1 rewrite note2 100 time notes 1. the prewrite time before erasure and the erase verify time (writeback time) are not included. 2. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. (2) serial write operation characteristics parameter symbol conditions min. typ. max. unit time from reset to flmd0 count start t rfcf t.b.d 10 t.b.d ms count execution time t count t.b.d 10 t.b.d ms flmd0 counter high-/low-level width t ch /t cl tc x 0.45 s flmd0 counter rise/fall time t r /t f 12.5 s remark these values may change after evaluation. serial write operation reset flmd0 v dd 0 v v dd 0 v t rfcf t cl t f t r t count t ch t c
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 windows and windows nt are either registered trad emarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. superflash ? is a registered trademark of silic on storage technology, inc. in several countries includin g the united states and ja p an.
?nec electronics corporation 2004 78k0/kd2 zud-cc-04-0127-e data published oct 2004 n cp(k) the information contained in this document is being issued in advance of the production cycle for the product. the parameters for the product may change before final production or nec electronics corporation, at its own discretion, may withdraw the product prior to its production. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special", and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics products before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m5 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": caution: this p roduct uses su p erflash ? technolo gy licensed from silicon stora g e technolo gy, inc.

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